Logic AND OR NOT Simulator
AND
1
OR
1
NOT A
0
How it works
AND, OR, and NOT are the three fundamental Boolean logic gates from which all digital circuits are built. These gates implement propositional logic in hardware: NOT inverts a signal, AND requires all inputs to be HIGH for output HIGH, OR requires any input HIGH for output HIGH.
**Truth tables** NOT: out = !A. Two-input AND: out = A·B (HIGH only when A=1 and B=1). Two-input OR: out = A+B (HIGH when A=1, B=1, or both). These truth tables define every possible output for every input combination. For n inputs, there are 2ⁿ rows in the truth table.
**NAND and NOR as universal gates** NAND (NOT-AND) and NOR (NOT-OR) are universal gates — any logic function can be implemented with only NAND gates or only NOR gates. This property makes them valuable in digital IC design: a single gate type can implement any logic, simplifying manufacturing.
**Practical logic families** TTL (Transistor-Transistor Logic): 5V supply, fast switching, moderate power. CMOS: 3.3V, 5V, or 1.8V supply, very low power (nW at standby), widely used in microcontrollers and FPGAs. Open-drain/open-collector outputs allow wire-AND connections and level shifting. Logic levels must be compatible — mixing TTL and CMOS inputs/outputs requires level translators.
**Propagation delay** Logic gates are not instantaneous — they have propagation delay (nanoseconds to picoseconds). In high-speed digital circuits, propagation delays determine maximum clock frequency. Hazards (glitches) in combinational logic occur when timing paths through the circuit have different delays — synthesis tools and hazard filtering eliminate most production problems.
Frequently Asked Questions
- AND: output HIGH only when all inputs are HIGH. OR: output HIGH when any input is HIGH. NAND: NOT-AND — output LOW only when all inputs are HIGH (complement of AND). NOR: NOT-OR — output LOW when any input is HIGH (complement of OR). NAND and NOR are 'universal gates' — any logic function can be built with only NAND gates or only NOR gates. This matters for chip design: a single gate type simplifies fabrication. In CMOS technology, NAND gates are also faster and more compact than AND gates because AND requires a NAND plus an inverter.
- A standard two-way switch circuit needs: light ON when either switch 1 XOR switch 2 is in the 'up' position (XOR logic — light is on when switches disagree). For more switches: use cascaded XOR gates. This is why a house wiring three-way switch circuit can be thought of as XOR logic (though implemented with physical crossover wires, not silicon gates). If you want light on when both switches are pressed (doorbell with two call buttons): that's OR logic. If you need both pressed simultaneously: AND logic.
- Fan-out is the number of gate inputs that one gate output can reliably drive. TTL logic: fan-out of 10 (one output drives up to 10 same-family inputs). CMOS: much higher fan-out (50–100+) due to low input current. Exceeding fan-out causes: output voltage levels to shift outside valid logic levels, increased propagation delay, and potential circuit failure. For large fan-out requirements: use buffer gates (high current drive), bus drivers, or multiple gate outputs in parallel (with resistors to prevent fighting). High fan-out is a common cause of intermittent failure in handbuilt digital circuits.
- Boolean minimization reduces circuit complexity. Key identities: A·A = A, A+A = A (idempotent), A·Ā = 0, A+Ā = 1 (complement), A·(A+B) = A (absorption). Example: F = AB + AB̄ = A(B + B̄) = A×1 = A — two AND gates reduce to a wire. For multiple variables (3–4 variables), Karnaugh maps group adjacent minterms in powers of 2 — each group corresponds to a simplified term. For 5+ variables, Quine-McCluskey algorithm is used. Minimized functions reduce gate count, power consumption, and propagation delay.